SH7080_09 Datasheet, PDF (304/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
0
HIZCNT
0
R/W Hi-Z Control
Specifies the state in software standby mode and when
bus mastership is released for CKE, RASU, RASL,
CASU, and CASL.
0: High impedance in software standby mode and when
bus mastership is released for CKE, RASU, RASL,
CASU, and CASL.
1: Driven in software standby mode and when bus
mastership is released for CKE, RASU, RASL,
CASU, and CASL.
9.4.2 CSn Space Bus Control Register (CSnBCR) (n = 0 to 8)
CSnBCR is a 32-bit readable/writable register that specifies the type of memory connected to the
respective space, the data bus width of the space, and the number of wait cycles between access
cycles.
Do not access external memory other than area 0 until the register initialization is complete.
Bit: 31
-
Initial value: 0
R/W: R
30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
IWW[1:0]
-
IWRWD[1:0]
-
IWRWS[1:0]
-
IWRRD[1:0]
-
IWRRS[1:0]
0
1
1
0
1
1
0
1
1
0
1
1
0
1
1
R R/W R/W R R/W R/W R R/W R/W R R/W R/W R R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
TYPE[2:0]
-
BSZ[1:0]
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0 1* 1* 0
0
0
0
0
0
0
0
0
R/W: R R/W R/W R/W R R/W R/W R
R
R
R
R
R
R
R
R
Note: * When the on-chip ROM is disabled, CS0BCR samples the value input through the MD0 and MD1 external pins that
specify the bus width when a power-on reset is performed.
Bit
31, 30
Bit Name
⎯
Initial
Value R/W
All 0 R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 244 of 1558
REJ09B0181-0400