SH7080_09 Datasheet, PDF (1335/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
H'00000
EB0
H'01000
EB1
H'02000
EB2
H'03000
EB3
H'04000
EB4
H'05000
EB5
H'06000
EB6
H'07000
EB7
H'08000
Flash memory
(user MAT)
EB8 to EB11
This area is accessible as both a RAM
area and as a flash memory area.
H'FFFF8000
On-chip RAM
H'FFFF9FFF
H'FFFFA000
H'FFFFAFFF
On-chip RAM
H'3FFFF
H'FFFFBFFF
Figure 23.18 Example of Overlapped RAM Operation
(SH7083: 256-kbyte Flash Memory Version)
Figure 23.18 shows an example of an overlap on block area EB0 of the flash memory.
Emulation is possible for a single area selected from among the eight areas, from EB0 to EB7, of
the user MAT. The area is selected by the setting of the RAM2 to RAM0 bits in RAMER.
1. To overlap a part of the RAM on area EB0, to allow realtime programming of the data for this
area, set the RAMS bit in RAMER to 1, and each of the RAM2 to RAM0 bits to 0.
2. Realtime programming is carried out using the overlaid area of RAM.
In programming or erasing the user MAT, it is necessary to run a program that implements a series
of procedural steps, including the downloading of an on-chip program. In this process, set the
download area with FTDAR so that the overlaid RAM area and the area where the on-chip
program is to be downloaded do not overlap.
Figure 23.19 shows an example of programming data that has been emulated to the EB0 area in
the user MAT.
Rev. 4.00 Dec. 15, 2009 Page 1275 of 1558
REJ09B0181-0400