SH7080_09 Datasheet, PDF (430/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5.13 Bus Arbitration
This LSI owns the bus mastership in normal state and releases the bus only when receiving a bus
request from an external device. This LSI has three bus masters: CPU, DMAC, and DTC. The bus
mastership is given to these bus masters in accordance with the following priority.
Request for bus mastership by external device (BREQ) > CPU > DTC > DMAC > CPU.
However, when DTC or DMAC is requesting the bus mastership, the CPU does not obtain the bus
mastership continuously.
The following cases should be noted regarding the external space access request from the CPU.
1. When the CSSTP2 bit is 1 in the bus function extending register (BSCHER), the external
space access request from the CPU has lower priority than the burst transfer request from the
DMAC and DTC transfer request with DTLOCK = 0 in the bus function extending register
(BSCHER).
2. When an activation request is generated in the order of DMAC and DTC while an external
space is being accessed by the CPU, DMA transfer is executed first and then DTC transfer.
Figure 9.49 shows the bus arbitration when the DTC and DMAC compete while an external
space is accessed by the CPU.
Rev. 4.00 Dec. 15, 2009 Page 370 of 1558
REJ09B0181-0400