SH7785 Datasheet, PDF (97/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Pipelining
(1-1) BF, BF/S, BT, BT/S, BRA, BSR:1 issue cycle + 0 to 3 branch cycles
I1 I2 I3 ID E1/S1 E2/s2 E3/s3 WB Note: In branch instructions that are categorized
as (1-1), the number of branch cycles
may be reduced by prefetching.
(I1) (I2) (I3) (ID)
(1-2) JSR, JMP, BRAF, BSRF: 1 issue cycle + 4 branch cycles
I1 I2 I3 ID E1/S1 E2/S2 E3/S3 WB
(Branch destination instruction)
(I1) (I2) (I3) (ID)
(Branch destination instruction)
(1-3) RTS: 1 issue cycle + 0 to 4 branch cycles
I1 I2 I3 ID E1/S1 E2/S2 E3/S3 WB
Note: The number of branch cycles may be
0 by prefetching instruction.
(I1) (I2) (I3) (ID)
(1-4) RTE: 4 issue cycles + 2 branch cycles
I1 I2 I3 ID s1 s2 s3 WB
ID E1s1 E2s2 E3s3 WB
ID
ID
(Branch destination instruction)
(I1) (I2) (I3) (ID) (Branch destination instruction)
(1-5) TRAPA: 8 issue cycles + 5 cycles + 2 branch cycle
I1 I2 I3 ID S1 S2 S3 WB
ID E1s1 E2s2 E3s3 WB
Note: It is 15 cycles to the ID stage
in the first instruction of exception handler
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
ID E1s1 E2s2 E3s3 WB
(I1) (I2) (I3) (ID)
(1-6) SLEEP: 2 issue cycles
I1 I2 I3 ID
S1 S2 S3 WB
ID E1s1 E2s2 E3s3 WB
Note: It is not constant cycles to
the clock halted period.
Figure 4.2 Instruction Execution Patterns (1)
Rev.1.00 Jan. 10, 2008 Page 67 of 1658
REJ09B0261-0100