SH7785 Datasheet, PDF (519/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit
Bit Name
23 to 20 ⎯
Initial
Value
All 0
19 to 16 TRAS3 to 0011
TRAS0
15
⎯
0
12. DDR2-SDRAM Interface (DBSC2)
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W tRAS (ACT-PRE period) Setting Bits
These bits set the ACT-PRE minimum period constraint
for the same bank. These bits should be set according
to the DDR2-SDRAM specifications. The number of
cycles is the number of DDR clock cycles.
0000: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
0010: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
0011: 4 cycles
0100: 5 cycles
:
1110: 15 cycles
1111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Rev.1.00 Jan. 10, 2008 Page 489 of 1658
REJ09B0261-0100