SH7785 Datasheet, PDF (316/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(6) Interrupt Mask Register 1 (INTMSK1)
INTMSK1 is a 32-bit readable and conditionally writable register that sets masking for IRL
interrupt requests. To clear the mask setting for the interrupt, write 1 to the corresponding bit in
INTMSKCLR1. Writing 0 to the bits in INTMSK1 has no effect. By reading this register once
after writing to this register or after clearing the mask by setting IMTMSKCLR1, the time length
necessary for reflecting the register value can be assured (the value read is reflected to the mask
status).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM10 IM11 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value: 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Name
31
IM10
30
IM11
29 to 24 ⎯
23 to 0 ⎯
Initial
Value
1
1
All 1
All 0
R/W Description
R/W Mask setting for all IRL3 to [When read]
IRL0 interrupt sources
when pins IRQ/IRL3 to
IRQ/IRL0 operate as an
encoded interrupt input.
0: The interrupt is
accepted.
1: The interrupt is
masked.
R/W Mask setting for all IRL7 to _{[When written]}
IRL4 interrupt sources
when pins IRQ/IRL7 to
0: No effect
IRQ/IRL4 operate as an ^{1: Masks the interrupt}
encoded interrupt input.
R
Reserved
These bits are always read as 1. The write value
should always be 1.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 286 of 1658
REJ09B0261-0100