SH7785 Datasheet, PDF (373/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
10.7 Usage Notes
10.7.1 Example of Handing Routine of IRL Interrupts and Level Detection IRQ
Interrupts when ICR0.LVLMODE = 0
When ICR0.LVLMODE is 0, IRL interrupt requests and level detection IRQ interrupt requests
that the INTC retains should be cleared in the interrupt handling routine because the CPU detects
after accepting interrupts. The IRQ interrupt sources (INTREQ) should also be cleared.
Start of IRQ level-sense or IRL
level-encoded interrupt handling
Interrupt handling
Instruct the external device to cancel
the IRQ/IRL level interrupt request by
using the GPIO output or writing to an
address in the local bus
1) Write to the GPIO register or local
bus space.
2) Read from the address that has been
written to.
Wait until the interrupt request signal
input on the IRL/IRQ pin is negated
and the INTC detects the negation
(at least 8 bus-clock cycles are
required)
Clear the IRQ/IRL level interrupt
request holding in the detection circuit
and clear the IRQ interrupt source
1) Set the corresponding bit in
INTMSK0/1 to 1.
2) Set the corresponding bit in
INTMSKCLR0/1 to 1.
3) Read INTMSK0/1.
End of IRQ/IRL level
interrupt handling
Figure 10.6 Example of Interrupt Handling Routine
Canceling the IRL interrupt request and level detection IRQ interrupt request that the CPU accepts
should be notified to the external device in the interrupt handling routine. For example, output the
data that can identify the accepted level and pins to the GPIO pin, or read the specific address. In
this case, write to the GPIO register and the local bus space, and read the same address
continuously.
To clear an interrupt request that is retained in the INTC, the wait time that the CPU detects the
cleared interrupt request is required. To guarantee the wait time, write to INTMSK0, INTMSK1,
INTMSKCLR0, and INTMSKCLR1, and read from INTMSK0 continuously.
Rev.1.00 Jan. 10, 2008 Page 343 of 1658
REJ09B0261-0100