SH7785 Datasheet, PDF (1051/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
Table 20.9 shows estimated image generation sequence shown in figure 20.6.
No. in the table corresponds to the number used in figure 20.6.
Table 20.9 Estimated Image Generation Sequence
No. Operation Description
(1) Calculation of The following formulae are used to compute output position (first row) (DDR2-
output position SDRAM output address).
(first row)
First row output address formulae
• Y output target address
Calculation formula: Output frame Y point value (base point) + [mbrow ×
16 × (width + Y padding)] + [mbcol × 16]
Output frame Y pointer value (base point): MCOYPR setting address
mbrow: Calculated from MCCF setting
mbcol: Calculated from MCCF setting
width: Calculated from MCWR setting
Y padding: Calculated from MCYPR setting
Subsequently, data for 16 dots (= 16 bytes) is processed in succession
• U/V output target address
Calculation formula: Output frame U point value (base point) + [mbrow × 8
× (width/2 + U padding)] + [mbcol × 8]
Output frame U pointer value (base point): MCOUPR setting address
mbrow: Calculated from MCCF setting
mbcol: Calculated from MCCF setting
width: Calculated from MCWR setting
U padding: Calculated from MCUVPR setting
Subsequently, data for 8 dots (= 8 bytes) is processed in succession
V pointer address is calculated using a formula similar to that for the U pointer
address.
Rev.1.00 Jan. 10, 2008 Page 1021 of 1658
REJ09B0261-0100