SH7785 Datasheet, PDF (1014/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.6 GA CL Input Data Alignment Register (DRCL_CTL)
DRCL_CTL is in the GDTA common register block and specifies data alignment of CL input
data.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
DCLR_
DTAM
DCLR_DTSA
DCLR_DTUA
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W
Initial
Bit
Bit Name
Value R/W Description
31 to 5 ⎯
All 0 ⎯
Reserved
These bits are always read as 0. The write value should
always be 0.
4
DCLR_DTAM 0
R/W Specifies data alignment conversion mode.
0: Data alignment is performed using an endian signal
1: Data alignment is performed using the DRCL_CTL
register setting
3, 2 DCLR_DTSA 0
R/W Specifies the data size for data alignment conversion.
00: No conversion
01: 64 bits
10: 32 bits
11: 16 bits
1, 0 DCLR_DTUA 0
R/W Specifies the unit for data alignment conversion.
00: No conversion
01: 8 bits
10: 16 bits
11: 32 bits
Note: For details of data alignment conversion patterns, refer to section 20.6, Data Alignment.
Rev.1.00 Jan. 10, 2008 Page 984 of 1658
REJ09B0261-0100