SH7785 Datasheet, PDF (740/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

14. Direct Memory Access Controller (DMAC)
Table 14.10 DMA Transfer Directions for On-Chip Peripheral Module Request*²*³
Transfer Destination
Transfer Source
LBSC
Space
DBSC
Space
PCIC Space
On-Chip
Peripheral
Module*¹
L or U
Memory
LBSC Space
N
N
N
Y
N
DBSC Space
N
N
N
Y
N
PCIC Space
N
N
N
Y
N
On-Chip Peripheral
Y
Y
Y
Module*¹
Y
Y
L or U Memory
N
N
N
Y
N
Legend:
Y: Transfer is enabled.
N: Transfer is disabled.
Notes: 1. This is the access size that is permitted by a register when the transfer source or
destination is an on-chip peripheral module.
2. The transfer source or destination must be the request source register for an on-chip
peripheral module request.
3. Only cycle steal mode can be set.
Rev.1.00 Jan. 10, 2008 Page 710 of 1658
REJ09B0261-0100