SH7785 Datasheet, PDF (1502/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

29. User Break Controller (UBC)
29.2.9 Break Control Register (CBCR)
CBCR is a readable/writable 32-bit register which specifies whether or not to use the user break
debugging support function. For details on the user break debugging support function, refer to
section 29.4, User Break Debugging Support Function.
Bit : 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R
Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UBDE
Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W: R R R R R R R R R R R R R R R R/W
Initial
Bit
Bit Name Value
31 to 1 —
All 0
0
UBDE
0
R/W Description
R Reserved
For read/write in this bit, refer to General Precautions on
Handling of Product.
R/W User Break Debugging Support Function Enable
Specifies whether or not to use the user break debugging
support function.
0: Does not use the user break debugging support
function.
1: Uses the user break debugging support function.
Rev.1.00 Jan. 10, 2008 Page 1472 of 1658
REJ09B0261-0100