SH7785 Datasheet, PDF (394/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

11. Local Bus State Controller (LBSC)
11.4.1 Memory Address Map Select Register (MMSELR)
MMSELR is a 32-bit register that selects memory address maps for areas 2 to 5. This register
should be accessed at the address H'FC40 0020 in longword. To prevent incorrect writing, writing
is accepted only when the upper 16-bit data is H'A5A5. The upper 29 bits are always read as 0.
This register is initialized to H'0000 0000 by a power-on reset or a manual reset.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Code for writing (H'A5A5)
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
2
1
0
AREASEL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R/W R/W R/W
Bit
Bit Name
31 to 16 (Code for
writing)
15 to 3 ⎯
Initial
Value R/W
All 0 R/W
All 0 R
Description
Code for writing
Set these bits to H'A5A5 (write H'A5A5 to these bits)
when writing to AREASEL (bits 2 to 0) in this register.
These bits are always read as 0.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 364 of 1658
REJ09B0261-0100