SH7785 Datasheet, PDF (1331/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

26. Serial Sound Interface (SSI) Module
26.3.1 Control Register (SSICR)
SSICR is a 32-bit readable/writable register that controls interrupts, selects each polarity status,
and sets operating mode.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯
⎯ DMEN UIEN OIEN IIEN DIEN CHNL1 CHNL0 DWL2 DWL1 DWL0 SWL2 SWL1 SWL0
Initial value: ⎯ ⎯
R/W: R R
⎯0
000
0
0
00
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SCKD SWSD SCKP SWSP SPDP SDTA PDTA
Initial value: 0 0
0
0
000
R/W: R/W R/W R/W R/W R/W R/W R/W
DEL
0
R/W
BREN CKDV2 CKDV1 CKDV0 MUEN CPEN TRMD
0
00
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W
EN
0
R/W
Initial
Bit
Bit Name Value R/W Description
31 to 29 ⎯
0
R
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
28
DMEN
0
R/W DMA Enable
Enables or disables the DMA request.
0: DMA request disabled.
1: DMA request enabled.
27
UIEN
0
R/W Underflow Interrupt Enable
0: Underflow interrupt disabled
1: Underflow interrupt enabled
26
OIEN
0
R/W Overflow Interrupt Enable
0: Overflow interrupt disabled
1: Overflow interrupt enabled
25
IIEN
0
R/W Idle Mode Interrupt Enable
0: Idle mode interrupt disabled
1: Idle mode interrupt enabled
24
DIEN
0
R/W Data Interrupt Enable
0: Data interrupt disabled
1: Data interrupt enabled
Rev.1.00 Jan. 10, 2008 Page 1301 of 1658
REJ09B0261-0100