SH7785 Datasheet, PDF (1270/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
24.6 Operations when Using DMA
24.6.1 Operation in Read Sequence
In order to transfer data in FIFO with the DMAC, set MMCIF (DMACR) after setting the
DMAC*. Transmit the read command after setting DMACR.
Figure 24.22 to 24.24 shows the operational flow for a read sequence.
• Clear FIFO and make settings in DMACR.
• Read command transmission is started.
• Command response is received from the card.
• Read data is received from the card.
• After the read sequence, data remains in FIFO. If necessary, write 100 to SET[2:0] in DMACR
to read all data from FIFO.
• Confirm that the DMAC transfer is completed and set the DMAEN bit in DMACR to 0.
• Set the CMDOFF bit to 1 and clear DMACR to H'00 if a CRC error (CRCERI) or a command
timeout error (CTERI) occurs in the command response reception.
• Set the CMDOFF bit to 1, clear DMACR to H'00, and clear FIFO if a CRC error (CRCERI) or
a data timeout error (DTERI) occurs in the read data reception.
When using DMA, next block read is resumed automatically when the AUTO bit in DMACR is
set to 1 and normal read is detected after the block transfer end of a pre-defined multiple block
transfer. Figure 24.25 shows the operational flow for a pre-defined multiple block read using auto-
mode.
• Clear FIFO.
• Set the block number to (TBNCR).
• Set DMACR.
• Read command transmission is started.
• Command response is received from the card.
• Read data is received from the card.
• Detect the command timeout error (CTERI) if a command response is not received from the
card.
• The end of the command sequence is detected by poling the BUSY flag in CSTR or through
the pre-defined multiple block transfer end flag (BTI).
Rev.1.00 Jan. 10, 2008 Page 1240 of 1658
REJ09B0261-0100