SH7785 Datasheet, PDF (801/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
16.4.2 Using Watchdog Timer Mode
1. Set the WDTCNT overflow time in WDTST.
2. Set the WT/IT bit in WDTCSR to 1, and select the type of reset with the RSTS bit.
3. When the TME bit in WDTCSR is set to 1, the WDT counter starts.
4. In watchdog timer mode, clear the WDTCNT or WDTBCNT periodically so that WDTCNT
does not overflow. See section 16.4.5, Clearing WDT Counters, for how to clear the WDT
counter.
5. When the WDTCNT overflows, the WDT sets the WOVF flag in WDTCSR to 1, and
generates a reset of the type specified by the RSTS bit. After the reset state is exited,
WDTCNT and WDTBCNT start counting again.
16.4.3 Using Interval Timer Mode
In interval timer mode, the WDT generates an interval timer interrupt each time the counter
overflows. This allows interrupt generation at regular intervals.
1. Set the WDTCNT overflow time in WDTST.
2. Clear the WT/IT bit in WDTCSR to 0.
3. When the TME bit in WDTCSR is set to 1, the WDT counter starts.
4. When the WDTCNT overflows, the WDT sets the IOVF flag in WDTCSR to 1, generating an
interval timer interrupt (ITI) request. WDTCNT and WDTBCNT continue counting.
Rev.1.00 Jan. 10, 2008 Page 771 of 1658
REJ09B0261-0100