SH7785 Datasheet, PDF (1185/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

23. Serial Peripheral Interface (HSPI)
23.3.1 Control Register (SPCR)
SPCR is a 32-bit readable/writable register that controls the transfer data of shift timing and
specifies the clock polarity and frequency.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— — — — — — — — FBS CLKP IDIV CLKC4 CLKC3 CLKC2 CLKC1 CLKC0
Initial value: ₀
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 8
Bit Name
⎯
Initial
Value
All 0
7
FBS
0
6
CLKP
0
R/W Description
R
Reserved
These bits are always read as an undefined value. The
write value should always be 0.
R/W First Bit Start
Controls the timing relationship between each bit of
transferred data and the serial clock.
0: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the first edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low. Similarly the first received bit
is sampled at the first edge of HSPI_CLK after the
HSPI_CS pin goes low.
1: The first bit transmitted from the HSPI module is set
up such that it can be sampled by the receiving device at
the second edge of HSPI_CLK after the HSPI_CS pin
goes low. Similarly the first received bit is sampled at the
second edge of HSPI_CLK specified by the register after
the HSPI_CS pin goes low.
R/W Serial Clock Polarity
0: HSPI_CLK signal is not inverted and so is low when
inactive.
1: HSPI_CLK signal is inverted and so is high when
inactive.
Rev.1.00 Jan. 10, 2008 Page 1155 of 1658
REJ09B0261-0100