SH7785 Datasheet, PDF (1212/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
Initial
Bit
Bit Name Value R/W Description
5
FIFO_EMPTY 0
R
FIFO Empty
This bit is set to 1 when the FIFO becomes empty while
data is being sent to the card, and cleared to 0 when
DATA_EN is set to 1 or the command sequence is
completed.
Indicates whether the FIFO holds data or not.
0: The FIFO includes data.
1: The FIFO is empty.
4
CWRE
0
R
Command Register Write Enable
Indicates whether the CMDR command is being
transmitted or has been transmitted.
0: The CMDR command has been transmitted, or the
CMDSTART bit in CMDSTRT has not been set yet,
so the new command can be written.
1: The CMDR command is waiting for transmission or is
being transmitted. If a new command is written, a
malfunction will result.
3
DTBUSY 0
R
Data Busy
Indicates command execution status. Indicates that the
card is in the busy state after the command sequence
of a command without data transfer which includes the
busy state in the response, or a command with write
data has been ended.
0: Idle state waiting for a command, or command
sequence execution in progress
1: Card is in the data busy state after command
sequence termination.
2
DTBUSY_TU Undefined R
Data Busy Pin Status
Indicates the MMCDAT pin level. By reading this bit, the
MMCDAT level can be monitored.
0: A low level is input to the MMCDAT pin.
1: A high level is input to the MMCDAT pin.
1
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev.1.00 Jan. 10, 2008 Page 1182 of 1658
REJ09B0261-0100