SH7785 Datasheet, PDF (314/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(5) Interrupt Mask Register 0 (INTMSK0)
INTMSK0 is a 32-bit readable and conditionally writable register that sets masking for each of the
interrupt requests IRQn (n = 0 to 7). To clear the mask setting for an interrupt, write 1 to the
corresponding bit in INTMSKCLR0. Writing 0 to the bits in INTMSK0 has no effect. By reading
this register once after writing to this register or after clearing the mask by setting
IMTMSKCLR0, the time length necessary for reflecting the register value can be assured (the
value read is reflected to the mask status).
When using IRQ/IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4 pins for encoded IRL
interrupt inputs, write 1 to IM00 to IM03 or IM04 to IM07, respectively.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM00 IM01 IM02 IM03 IM04 IM05 IM06 IM07 ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
Initial value: 1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R R R R R
Bit
Name
31
IM00
30
IM01
29
IM02
28
IM03
27
IM04
Initial
Value R/W Description
1
R/W Sets masking of individual [When read]
pin interrupt source on
IRQ0.
0: The interrupts are
accepted.
1
R/W Sets masking of individual _{1: The interrupts are}
pin interrupt source on
masked.
IRQ1.
[When written]
1
R/W Sets masking of individual _{0: No effect}
pin interrupt source on
IRQ2.
1: Masks the interrupt
1
R/W Sets masking of individual
pin interrupt source on
IRQ3.
1
R/W Sets masking of individual
pin interrupt source on
IRQ4.
Rev.1.00 Jan. 10, 2008 Page 284 of 1658
REJ09B0261-0100