SH7785 Datasheet, PDF (597/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Bit
12
11
10, 9
8
7
Bit Name
RTA
STA
DEVSEL
MDPE
FBBC
Initial
Value
0
0
01
0
1
R/W
Description
SH: R/WC Target Abort Receive Status
PCI: R/WC This bit indicates that a transaction was completed by
target abort when the PCIC is a master.
0: Transaction is not completed with target abort
1: The bus master detected completion of transaction
with target abort.
SH: R/WC Target Abort Execution Status
PCI: R/WC This bit indicates that a transaction was completed by
target abort when the PCIC is a target.
0: Transaction is not completed by target abort
1: Transaction was completed by target abort
SH: R
DEVSEL Timing Status
PCI: R
This bit indicate the response timing status of
DEVSEL when the PCIC is a target.
00: Fast (not support)
01: Medium
10: Slow (not support)
11: Reserved
SH: R/WC Data Parity Error
PCI: R/WC This bit indicates that the PCIC asserted PERR or
detected the assertion of PERR when the PCIC is a
master. This bit is set to 1 only when the parity
response bit is set to 1.
0: Data parity error is not generated
1: Data parity error was generated
SH: R
PCI: R
Fast Back-to-Back Status
This bit indicates whether a target can accept fast
back-to-back transfers for a different target if the PCIC
is a target.
0: A target does not support fast back-to-back
transactions for a different target
1: A target supports fast back-to-back transactions for
a different target
Rev.1.00 Jan. 10, 2008 Page 567 of 1658
REJ09B0261-0100