SH7785 Datasheet, PDF (1154/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
Initial
Bit
Bit Name Value R/W Description
11 to 8 TDLA[3:0] 0000
R/W Transmit Left-Channel Data Assigns 3 to 0
These bits specify the position of left-channel data in a
transmit frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Transmit data for the left channel is specified in the
SITDL bit in SITDR.
7
TDRE
0
R/W Transmit Right-Channel Data Enable
0: Disables right-channel data transmission
1: Enables right-channel data transmission
6
TLREP
0
R/W Transmit Left-Channel Repeat
0: Transmits data specified in the SITDR bit in SITDR
as right-channel data
1: Repeatedly transmits data specified in the SITDL bit
in SITDR as right-channel data
• This bit setting is valid when the TDRE bit is set to
1.
• When this bit is set to 1, the SITDR settings are
ignored.
5, 4
—
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
3 to 0 TDRA[3:0] 0000
R/W Transmit Right-Channel Data Assigns 3 to 0
These bits specify the position of right-channel data in a
transmit frame as B'0000 (0) to B'1110 (14).
1111: Setting prohibited
• Transmit data for the right channel is specified in the
SITDR bit in SITDR.
Rev.1.00 Jan. 10, 2008 Page 1124 of 1658
REJ09B0261-0100