SH7785 Datasheet, PDF (523/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Bit
Bit Name
15 to 11 ⎯
Initial
Value
All 0
10 to 8 TRRD2 to 000
TRRD0
7 to 3 ⎯
All 0
12. DDR2-SDRAM Interface (DBSC2)
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
R/W tRRD (ACT(A)-ACT(B) period) Setting Bits
These bits set the ACT-ACT minimum period constraint
for the different banks. These bits should be set
according to the DDR2-SDRAM specifications. The
number of cycles is the number of DDR clock cycles.
000: 1 cycle
001: 2 cycles
010: 3 cycles
011: 4 cycles
100: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
:
111: Setting prohibit (If specified, correct operation
cannot be guaranteed.)
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Rev.1.00 Jan. 10, 2008 Page 493 of 1658
REJ09B0261-0100