SH7785 Datasheet, PDF (106/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

4. Pipelining
4.2 Parallel-Executability
Instructions are categorized into six groups according to the internal function blocks used, as
shown in table 4.2. Table 4.3 shows the parallel-executability of pairs of instructions in terms of
groups. For example, ADD in the EX group and BRA in the BR group can be executed in parallel.
Table 4.2 Instruction Groups
Instruction
Group
EX
MT
BR
LS
ADD
ADDC
ADDV
AND #imm,R0
AND Rm,Rn
CLRMAC
CLRS
CLRT
CMP
DIV0S
DIV0U
DIV1
DMUS.L
DMULU.L
MOV #imm,Rn
BF
BF/S
BRA
FABS
FNEG
FLDI0
FLDI1
FLDS
FMOV @adr,FR
FMOV FR,@adr
FMOV FR,FR
FMOV.S @adr,FR
Instruction
DT
EXTS
EXTU
MOVT
MUL.L
MULS.W
MULU.W
NEG
NEGC
NOT
OR #imm,R0
OR Rm,Rn
ROTCL
ROTCR
ROTL
ROTR
SETS
SETT
SHAD
SHAL
SHAR
SHLD
SHLL
SHLL2
SHLL8
SHLL16
SHLR
SHLR2
MOV Rm,Rn
NOP
BRAF
BSR
BSRF
BT
BT/S
JMP
FMOV.S FR,@adr
FSTS
LDC Rm,CR1
LDC.L @Rm+,CR1
LDS Rm,SR1
LDS Rm,SR2
LDS.L @adr,SR2
LDS.L @Rm+,SR1
LDS.L @Rm+,SR2
MOV.[BWL] @adr,R
MOV.[BWL] R,@adr
MOVA
MOVCA.L
MOVUA
OCBI
OCBP
OCBWB
PREF
SHLR8
SHLR16
SUB
SUBC
SUBV
SWAP
TST #imm,R0
TST Rm,Rn
XOR #imm,R0
XOR Rm,Rn
XTRCT
JSR
RTS
STC CR2,Rn
STC.L CR2,@-Rn
STS SR2,Rn
STS.L SR2,@-Rn
STS SR1,Rn
STS.L SR1,@-Rn
Rev.1.00 Jan. 10, 2008 Page 76 of 1658
REJ09B0261-0100