SH7785 Datasheet, PDF (140/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Handling
ITLB_protection_violation_exception()
{
TEA = EXCEPTION_ADDRESS;
PTEH.VPN = PAGE_NUMBER;
SPC = PC;
SSR = SR;
SGR = R15;
EXPEVT = H'0000 00A0;
SR.MD = 1;
SR.RB = 1;
SR.BL = 1;
PC = VBR + H'0000 0100;
}
(6) Data Address Error
• Sources:
⎯ Word data access from other than a word boundary (2n +1)
⎯ Longword data access from other than a longword data boundary (4n +1, 4n + 2, or 4n +3)
(Except MOVLIA)
⎯ Quadword data access from other than a quadword data boundary (8n +1, 8n + 2, 8n +3, 8n
+ 4, 8n + 5, 8n + 6, or 8n + 7)
⎯ Access to area H'80000000 to H'FFFFFFFF in user mode
Areas H'E0000000 to H'E3FFFFFF and H'E5000000 to H'E5FFFFFF can be accessed in
user mode. For details, see section 7, Memory Management Unit (MMU) and section 9,
On-Chip Memory.
⎯ The MMCAW bit in EXPMASK is 0, and the IC/OC memory mapped associative write is
performed. For details of memory mapped associative write, see section 8.6.5, Memory-
Mapped Cache Associative Write Operation.
• Transition address: VBR + H'0000100
Rev.1.00 Jan. 10, 2008 Page 110 of 1658
REJ09B0261-0100