SH7785 Datasheet, PDF (501/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Access Size
Quadword
12. DDR2-SDRAM Interface (DBSC2)
Address
Address 0
(First access:
address 4)
Address 0
(Second access:
Address 0)
MDQ31 to
MDQ24
Data
63 to 56
Data
31 to 24
MDQ23 to
MDQ16
Data
55 to 48
Data
23 to 16
MDQ15 to
MDQ8
Data
47 to 40
Data
15 to 8
MDQ7 to
MDQ0
Data
39 to 32
Data
7 to 0
Table 12.6 Data Alignment for Access in Big Endian when External Data Bus Width Is Set
to 32 Bits
Access Size
Byte
Address
Address 0
Address 1
Address 2
Address 3
Address 4
Address 5
Address 6
Address 7
MDQ31 to
MDQ24
Data
7 to 0
Data
7 to 0
MDQ23 to
MDQ16
Data
7 to 0
Data
7 to 0
MDQ15 to
MDQ8
Data
7 to 0
Data
7 to 0
MDQ7 to
MDQ0
Data
7 to 0
Data
7 to 0
Rev.1.00 Jan. 10, 2008 Page 471 of 1658
REJ09B0261-0100