SH7785 Datasheet, PDF (657/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
(26) PCI Cache Snoop Address Register 0 (PCICSAR0)
This register specifies the address to be compared with the PCI address requested by an external
PCI device to the PCIC. For details, see section 13.4.4 (7), Cache Coherency.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CADR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
CADR
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
PCI R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
31 to 0
Initial
Bit Name Value R/W
CADR
H'0000 SH: R/W
0000 _{PCI: R/W}
Description
Address to be Compared
This register specifies the address to be compared
with the SuperHyway bus address that is requested
by an external device to the PCI
Rev.1.00 Jan. 10, 2008 Page 627 of 1658
REJ09B0261-0100