SH7785 Datasheet, PDF (164/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

6. Floating-Point Unit (FPU)
Bit
Bit Name
17 to 12 Cause
11 to 7 Enable
6 to 2 Flag
Initial
Value
All 0
All 0
All 0
1
RM1
0
0
RM0
1
R/W Description
R/W FPU Exception Cause Field
R/W ^{FPU Exception Enable Field}
R/W ^{FPU Exception Flag Field}
Each time an FPU operation instruction is executed, the
FPU exception cause field is cleared to 0. When an
FPU exception occurs, the bits corresponding to FPU
exception cause field and flag field are set to 1. The
FPU exception flag field remains set to 1 until it is
cleared to 0 by software.
For bit allocations of each field, see table 6.3.
R/W Rounding Mode
R/W These bits select the rounding mode.
00: Round to Nearest
01: Round to Zero
10: Reserved
11: Reserved
Rev.1.00 Jan. 10, 2008 Page 134 of 1658
REJ09B0261-0100