SH7785 Datasheet, PDF (1393/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
27.3.13 Transfer Control Register (FLTRCR)
Setting the TRSTRT bit to 1 starts access to flash memory. The completion of the access can be
checked by the TREND bit.
Bit: 7
6
5
4
3
2
1
0
TREND TRSTRT
Initial value: 0
0
0
0
0
0
0
0
R/W: R R R R R R R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 2 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
TREND 0
R/W Processing End Flag
Indicates that the processing performed in the specified
access mode has been completed. The write value
should always be 0.
0
TRSTRT 0
R/W Transfer Start
When the TREND bit is 0, processing in the access mode
specified by the access mode specification bits ACM[1:0]
is started by setting the TRSTRT bit from 0 to 1.
0: Stops transfer
1: Starts transfer
Rev.1.00 Jan. 10, 2008 Page 1363 of 1658
REJ09B0261-0100