SH7785 Datasheet, PDF (1406/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

27. NAND Flash Memory Controller (FLCTL)
27.6 Interrupt Processing
The FLCTL has four interrupt sources. Each of the interrupt sources has its corresponding
interrupt flag. The interrupt request is generated independently if the interrupt is enabled by the
interrupt enable bit. The status error and ready/busy timeout error use the common FLSTE
interrupt.
Table 27.6 FLCTL Interrupt Requests
Interrupt Source
FLSTE interrupt
FLTEND interrupt
FLTRQ0 interrupt
FLTRQ1 interrupt
Interrupt Flag
STERB
BTOERB
TREND
TRREQF0
TRREQF1
Enable Bit
STERINTE
RBERINTE
TEINTE
TRINTE0
TRINTE1
Description
Status error
Ready/busy timeout error
Transfer end
FIFO0 transfer request
FIFO1 transfer request
27.7 DMA Transfer Settings
The FLCTL can request DMA transfers separately to the data sector, FLDTFIFO, and control
code sector, FLECFIFO. Table 27.7 shows whether DMA transfer is enabled or disabled in each
access mode.
Table 27.7 DMA Transfer Settings
FLDTFIFO
FLECFIFO
Sector Access Mode
Enabled
Enabled
Command Access Mode
Enabled
Disabled
For details on DMAC settings, see section 14, Direct Memory Access Controller (DMAC).
Rev.1.00 Jan. 10, 2008 Page 1376 of 1658
REJ09B0261-0100