SH7785 Datasheet, PDF (1112/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

21. Serial Communication Interface with FIFO (SCIF)
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
ER = 1?
Yes
Receive error handling
[1] Whether a framing error or parity error
has occurred in the receive data that
is to be read from SCFRDR can be
ascertained from the FER and PER
bits in SCFSR.
[2] When a break signal is received,
receive data (H'00) is not transferred
to SCFRDR.
However, note that the last data in
SCFRDR is H'00, and the break data
in which a framing error occurred is
stored.
When a break handling is completed
and a receive signal returns to 1, the
receive data transfer resumes.
No
BRK = 1?
Yes
Break handling
No
DR = 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags
in SCFSR,
and ORER flag in SCLSR, to 0
End
Figure 21.12 Sample Serial Reception Flowchart (2)
Rev.1.00 Jan. 10, 2008 Page 1082 of 1658
REJ09B0261-0100