SH7785 Datasheet, PDF (489/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 12.1 shows a block diagram of the DBSC2.
SuperHyway Bus
DBSC2
Request
queue
BUS IF
Write data
queue
12. DDR2-SDRAM Interface (DBSC2)
Response
queue
Registers
Control
unit
DDRPAD
DLL
IO cells
MCK0/
MCK0,
MCK1/
MCK1
MCKE, MA14 to MA0,
MBA2 to MBA0, MCS,
MRAS, MCAS, MWE,
MODT
MDQS3 to MDQS0,
MDQS3 to MDQS0,
MDM3 to MDM0,
MDQ31 to MDQ0
MBKPRST, MVREF
DDR2-SDRAM
Notes:
Request queue: Stores the access request of the SuperHyway bus.
Write data queue: Stores the write data sent from the SuperHyway bus.
Response queue: Stores the read data to be sent back to the SuperHyway bus.
Control unit:
Controls each block depending on the request sent from the request queue.
Registers:
Store timing parameters and SDRAM configuration information.
DDRPAD:
Interfaces with the DDR2-SDRAM. This incorporates the DLL
to perform phase adjustment of the DQS.
Figure 12.1 Block Diagram of the DBSC2
Rev.1.00 Jan. 10, 2008 Page 459 of 1658
REJ09B0261-0100