SH7785 Datasheet, PDF (1258/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
• The end of the command sequence is detected by poling the BUSY flag in CSTR, data transfer
end interrupt (DTI), data response interrupt (DRPI), or pre-defined multiple block transfer end
(BTI).
• The data busy state is checked through DTBUSY in CSTR. If the card is in data busy state, the
end of the data busy state is detected by the data busy end interrupt (DBSYI).
• Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a command timeout error (CTERI)
occurs in the command response reception.
• Write the CMDOFF bit to 1 if a CRC error (CRCERI) or a data timeout error (DTERI) occurs
in the write data transmission.
Note: In a write to the card by stream transfer, the MMCIF continues data transfer to the card
even after a FIFO empty interrupt is detected. In this case, complete the command
sequence after at least 24 transfer clock cycles.
Rev.1.00 Jan. 10, 2008 Page 1228 of 1658
REJ09B0261-0100