SH7785 Datasheet, PDF (951/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
19.3.52 External Synchronization Control Register (ESCR)
The external synchronization control register (ESCR) controls the dot clock.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
—
—
—
—
—
—
—
—
—
—
—
DCLK
SEL
—
—
—
DCLK
DIS
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R R R R/W
Internal update:
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
———————————
FRQSEL
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
Internal update:
Initial
Bit
Bit Name Value
31 to 21 ⎯
All 0
20
DCLKSEL 0
19 to 17 ⎯
All 0
16
DCLKDIS 0
15 to 5 ⎯
All 0
Internal
R/W Update Description
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W None
DOTCLKIN Select
To enable this bit, the DCKE bit in DEFR should
be set to 1. In the initial state, this bit is fixed to 0.
0: The input dot clock source is the DCLKIN pin
1: The input dot clock is DUck
This setting should be made such that the
frequency of the frequency-divided dot clock
generated by the dot clock generation circuit is
50 MHz or lower.
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W None
DOTCLKOUT Disable
0: DOTCLKOUT is output.
1: DOTCLKOUT is not output.
DOTCLKOUT is fixed to low level.
R
⎯
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev.1.00 Jan. 10, 2008 Page 921 of 1658
REJ09B0261-0100