SH7785 Datasheet, PDF (317/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

10. Interrupt Controller (INTC)
(7) Interrupt Mask Register 2 (INTMSK2)
INTMSK2 is a 32-bit readable and conditionally writable register that sets masking for IRL
interrupt requests for input level pattern on the IRL pins. To clear the mask setting for the
interrupt, write 1 to the corresponding bit in INTMSKCLR2. Writing 0 to the bits in INTMSK2
has no effect. By reading this register once after writing to this register or after clearing the mask
by setting IMTMSKCLR2, the time length necessary for reflecting the register value can be
assured (the value read is reflected to the mask status).
INTMSK2 settings are valid when the IRQ/IRL3 to IRQ/IRL0 pins or IRQ/IRL7 to IRQ/IRL4
pins are used for encoded IRL interrupt inputs, and the corresponding IRL interrupt is not masked
by INTMSK1.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IM015 IM014 IM013 IM012 IM011 IM010 IM009 IM008 IM007 IM006 IM005 IM004 IM003 IM002 IM001 ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
IM115 IM114 IM113 IM112 IM111 IM110 IM109 IM108 IM107 IM106 IM105 IM104 IM103 IM102 IM101 ⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Bit
Name
31
IM015
30
IM014
29
IM013
28
IM012
27
IM011
Initial
Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Description
Masks the interrupt source
of IRL3 to IRL0 = LLLL
(H'0).
Masks the interrupt source
of IRL3 to IRL0 = LLLH
(H'1).
Masks the interrupt source
of IRL3 to IRL0 = LLHL
(H'2).
[When read]
0: The interrupt is
accepted.
1: The interrupt is
masked.
[When written]
0: No effect
1: Masks the interrupt
Masks the interrupt source
of IRL3 to IRL0 = LLHH
(H'3).
Masks the interrupt source
of IRL3 to IRL0 = LHLL
(H'4).
Rev.1.00 Jan. 10, 2008 Page 287 of 1658
REJ09B0261-0100