SH7785 Datasheet, PDF (1680/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Appendix
Pin Name
Pin Name (LSI level) (Module level)
Module I/O
SCIF0_SCK/
HSPI_CLK/
FRE
Port H2 (default)
SCIF0_SCK
HSPI_CLK
GPIO I/O
SCIF
I/O
HSPI
I/O
FRE
FLCTL O
SCIF0_TXD/
HSPI_TX/
FWE
Port H0 (default)
SCIF0_TXD
HSPI_TX
GPIO I/O
SCIF
O
HSPI
O
FWE
FLCTL O
SCIF1_RXD
Port H6 (default)
GPIO I/O
SCIF1_RXD
SCIF
I
SCIF1_SCK
Port H7 (default)
GPIO I/O
SCIF1_SCK
SCIF
I/O
SCIF1_TXD
Port H5 (default)
GPIO I/O
SCIF1_TXD
SCIF
O
SCIF2_RXD/
SIOF_RXD
SCIF2_RXD (default) SCIF
I
SIOF_RXD
SIOF
I
SIOF_MCLK/
HAC_RES
Port J3 (default)
SIOF_MCLK
GPIO I/O
SIOF
I
HAC_RES
HAC
O
SIOF_RXD/
HAC0_SDIN/
SSI0_SCK
Port J5 (default)
SIOF_RXD
HAC0_SDIN
GPIO I/O
SIOF
I
HAC
I
SSI0_SCK
SSI
I/O
SIOF_SCK/
HAC0_BITCLK/
SSI0_CLK
Port J2 (default)
SIOF_SCK
HAC0_BITCLK
GPIO I/O
SIOF
I/O
HAC
I
SSI0_CLK
SSI
I
SIOF_SYNC/
HAC0_SYNC/
SSI0_WS
Port J4 (default)
SIOF_SYNC
HAC0_SYNC
GPIO I/O
SIOF
I/O
HAC
O
SSI0_WS
SSI
I/O
When Not in Use
Open
Open
Open
Open
Open
Open
Open
Open
Open
Open
Rev.1.00 Jan. 10, 2008 Page 1650 of 1658
REJ09B0261-0100