SH7785 Datasheet, PDF (1236/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
24.3.16 Data Register (DR)
DR is a register for reading/writing FIFO data.
Word/byte access is enabled to addresses of this register.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
DR
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 0 DR
Initial
Value
⎯
R/W Description
R/W Register for reading/writing FIFO data.
Word/byte access is enabled.
When DR is accessed in words, the upper and lower
bytes are transmitted or received in that order. Word
access and byte access can be done in random order.
However, (DR address + 1) cannot be accessed in
bytes.
The following shows examples of DR access.
When data is written to DR in the following steps 1 to 4, the transmit data is stored in the FIFO as
shown in figure 24.2.
1. Write word data H'0123 to DR.
2. Write byte data H'45 to DR.
3. Write word data H'6789 to DR.
4. Write byte data H'AB to DR.
When the receive data is stored in the FIFO as shown in figure 24.2 (for example, after data is
started to be received while the FIFO is empty and data is received in the order of H'01, H'23, ...,
H'AB), data can be read from DR in the following steps 5 to 8.
5. Read byte data H'01 from DR.
6. Read word data H'2345 from DR.
7. Read byte data H'67 from DR.
8. Read word data H'89AB from DR.
Rev.1.00 Jan. 10, 2008 Page 1206 of 1658
REJ09B0261-0100