SH7785 Datasheet, PDF (379/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

Figure 11.1 shows a block diagram of the LBSC.
11. Local Bus State Controller (LBSC)
RDY
Wait controller
Bus interface
CSnWCR
CS0 to CS6
CE2A to CE2B
BS
RD
R/W
WE7 to WE0
IORD, IOWR
REG
IOIS16
Area controller
Memory
controller
CSnBCR
BCR
CSnPCR
Legend:
CSnWCR: CSn wait control register (n = 0 to 6)
CSnBCR: CSn bus control register (n = 0 to 6)
BCR: Bus control register
CSnPCR: CSn PCMCIA control register (n = 5 and 6)
Figure 11.1 Block Diagram of LBSC
LBSC
Rev.1.00 Jan. 10, 2008 Page 349 of 1658
REJ09B0261-0100