SH7785 Datasheet, PDF (773/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

15. Clock Pulse Generator (CPG)
Initial
Bit
Bit Name Value R/W Description
31
IFC3
0
R/W Frequency division ratio of the CPU clock (Ick)
30
IFC2
0
R/W 0000: No change
29
IFC1
0
R/W 0001: × 1/2
28
IFC0
0
R/W 0010: × 1/4
0011: × 1/6
Others: Setting prohibited
27
UFC3
0
26
UFC2
0
25
UFC1
0
24
UFC0
0
R/W Frequency division ratio of the RAM clock (Uck)
R/W 0000: No change
R/W 0010: × 1/4
R/W 0011: × 1/6
Others: Setting prohibited
23
SFC3
0
22
SFC2
0
21
SFC1
0
20
SFC0
0
R/W Frequency division ratio of the SuperHyway clock
R/W ^(SHck)
R/W ^{0000: No change}
R/W ^{0010: × 1/4}
0011: × 1/6
Others: Setting prohibited
19
BFC3
0
18
BFC2
0
17
BFC1
0
16
BFC0
0
R/W Frequency division ratio of the bus clock (Bck)
R/W 0000: No change
R/W 0101: × 1/12
R/W 0110: × 1/16
0111: × 1/18
1000: × 1/24
1001: × 1/32
1010: × 1/36
1011: × 1/48
Others: Setting prohibited
15
MFC3
0
14
MFC2
0
13
MFC1
0
12
MFC0
0
R/W Frequency division ratio of the DDR clock (DDRck)
R/W 0000: No change
R/W 0010: × 1/4
R/W 0011: × 1/6
Others: Setting prohibited
Rev.1.00 Jan. 10, 2008 Page 743 of 1658
REJ09B0261-0100