SH7785 Datasheet, PDF (840/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

18. Timer Unit (TMU)
18.4 Operation
Each channel has a 32-bit timer counter (TCNT) and a 32-bit timer constant register (TCOR).
Each TCNT performs count-down operation. The channels have an auto-reload function that
allows cyclic count operations, and can also perform external event counting. Channel 2 also has
an input capture function.
18.4.1 Counter Operation
When one of bits STR0 to STR2 in TSTR is set to 1, the TCNT for the corresponding channel
starts counting. When TCNT underflows, the UNF flag in TCR is set. If the UNIE bit in TCR is
set to 1 at this time, an interrupt request is sent to the CPU. At the same time, the value is copied
from TCOR into TCNT, and the count-down continues (auto-reload function).
(1) Example of Counter Operation Setting Procedure
Figure 18.2 shows an example of the counter operation setting procedure.
Counter operation setup
Select counter clock
(1)
Set up underflow
interrupt generation
(2)
When using
input capture
function
Set up input capture
(3)
interrupt generation
Set timer constant
register
(4)
(1) Select the counter clock with the TPSC2 to TPSC0 bits
in TCR. When the external clock (TCLK) is selected,
specify the external clock edge with the CKEG1 and
CKEG0 bits in TCR.
(2) Specify whether an interrupt is generated on TCNT
underflow with the UNIE bit in TCR.
(3) When the input capture function is used, set the ICPE
bits in TCR, which also specify the use of the interrupt
function.
(4) Set a value in TCOR.
(5) Set the initial value in TCNT.
(6) Set the STR bit in TSTR to 1 to start counting.
Load the counter with
the initial value
(5)
Start counting
(6)
Note: When an interrupt is generated, clear the source flag in the interrupt handler processing.
If the interrupt is enabled without clearing the flag, another interrupt will be generated.
Figure 18.2 Example of Count Operation Setting Procedure
Rev.1.00 Jan. 10, 2008 Page 810 of 1658
REJ09B0261-0100