SH7785 Datasheet, PDF (1010/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.2 GA Enable Register (GACER)
GACER is in the GDTA common register block and controls the block operation.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ MC_EN CL_EN
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ R/W R/W
Bit
Bit Name
31 to 2 ⎯
1
MC_EN
0
CL_EN
Initial
Value
All 0
0
0
R/W Description
⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Enables access to the MC registers.
0: Writing to the MC registers is invalid. The value read
from the MC register is undefined.
1: Reading and writing are enabled.
R/W Enables access to the CL registers.
0: Writing to the CL registers is invalid. The value read
from the CL register is undefined.
1: Reading and writing are enabled.
Rev.1.00 Jan. 10, 2008 Page 980 of 1658
REJ09B0261-0100