SH7785 Datasheet, PDF (279/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

9. On-Chip Memory
Bit
5 to 0
Bit Name
L0SSZ
Initial
Value R/W
Undefined R/W
Description
OL memory Page 0 Block Transfer Source Address
Select
When MMUCR.AT = 0 or RAMCR.RP = 0, these bits
select whether the operand addresses or L0SADR
values are used as bits 15 to 10 of the transfer source
physical address for block transfer to page 0A or 0B in
the OL memory. L0SSZ[5:0] correspond to the transfer
source physical addresses [15:10].
0: The operand address is used as the transfer source
physical address.
1: The L0SADR value is used as the transfer source
physical address.
Settable values:
111111: Transfer source physical address is specified
in 1-Kbyte units.
111110: Transfer source physical address is specified
in 2-Kbyte units.
111100: Transfer source physical address is specified
in 4-Kbyte units.
111000: Transfer source physical address is specified
in 8-Kbyte units.
110000: Transfer source physical address is specified
in 16-Kbyte units.
100000: Transfer source physical address is specified
in 32-Kbyte units.
000000: Transfer source physical address is specified
in 64-Kbyte units.
Settings other than the ones given above are
prohibited.
Rev.1.00 Jan. 10, 2008 Page 249 of 1658
REJ09B0261-0100