SH7785 Datasheet, PDF (1300/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

25. Audio Codec Interface (HAC)
Bit
10
9
8 to 6
5
4 to 0
Initial
Bit Name Value R/W Description
WMRT
0
W
HAC Warm Reset
Use a warm reset only after power-up, or only to exit
from the power-down mode by the power-down
command.
[Write]
0: Always write 0 to this bit before writing 1 again.
(When this bit is changed from 0 to 1, a warm reset is
performed.)
1: Performs a warm reset on the HAC-connected
codec.
[Read]
Always read as 0.
⎯
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
ST
0
W
Start Transfer
[Write]
0: Stops data transmission/reception at the end of the
current frame. Do not take this action to terminate
transmission/reception in normal operation. When
terminating transmission/reception in normal
operation, refer to the following description.
1: Starts data transmission/reception.
[Read]
Always read as 0.
⎯
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
To place the off-chip codec device into the power-down mode, write 1 to bit 12 of the register
index 26 in the off-chip codec via the HAC. When entering the power-down mode, the off-chip
codec stops HAC_BITCLK and suspends the normal operation. The off-chip codec acts in the
same manner at power-on. To resume the normal operation, perform a cold reset or a warm reset
on the off-chip codec.
Rev.1.00 Jan. 10, 2008 Page 1270 of 1658
REJ09B0261-0100