SH7785 Datasheet, PDF (1617/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

32. Electrical Characteristics
Tm1 Tmd1
CLKOUT
RD/FRAME
D31 to D0
t_FMD
t_FMD
t_WDD
A
t_WDD
D0
t_WDD
CSn
RD/WR
WEn
RDY
BS
DACKn
(DA)
t_CSD
t_RWD
t_CSD
t_RWD
t_WED1
t_WED1
t_RDYS
t_BSD
t_RDYH
t_BSD
t_DACD
t_DACD
Tm1 Tmd1w Tmd1
t_FMD
t_FMD
t_WDD
A
t_CSD
t_WDD
D0
t_RWD
t_WDD
t_CSD
t_RWD
t_WED1
t_RDYS
t_BSD
t_BSD
t_WED1
t_RDYH
t_DACD
t_DACD
Tm1 Tmd1w Tmd1w Tmd1
t_FMD
t_FMD
t_WDD
A
t_CSD
t_WDD
D0
t_RWD
t_WDD
t_CSD
t_RWD
t_WED1
t_RDYS
t_RDYH
t_BSD
t_RDYS
t_BSD
t_WED1
t_RDYH
t_DACD
t_DACD
(1) 1st data: No wait
(2) 1st data: One internal wait cycle
Information in the first data bus cycle Information in the first data bus cycle
D31 to D29: Access size
D31 to D29: Access size
000:
Byte
000:
Byte
001:
Word (2 bytes)
001:
Word (2 bytes)
010:
Longword (4 bytes)
010:
Longword (4 bytes)
011:
Quadword (8 bytes)
011:
Quadword (8 bytes)
1xx:
Burst (32 bytes)
1xx:
Burst (32 bytes)
D25 to D0: Address
D25 to D0: Address
(3) 1st data: One internal wait + one external wait cycles
Information in the first data bus cycle
D31 to D29: Access size
000:
Byte
001:
Word (2 bytes)
010:
Longword (4 bytes)
011:
Quadword (8 bytes)
1xx:
Burst (32 bytes)
D25 to D0: Address
Legend:
IO: DACK device
SA: Single-address DMA transfer
DA: Dual-address DMA transfer
Note: DACK is configured as active-high.
Figure 32.21 MPX Basic Bus Cycle (Write)
Rev.1.00 Jan. 10, 2008 Page 1587 of 1658
REJ09B0261-0100