SH7785 Datasheet, PDF (1140/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

22. Serial I/O with FIFO (SIOF)
22.3.5 Transmit Control Data Register (SITCR)
SITCR is a 32-bit readable/writable register that specifies transmit control data of the SIOF. The
setting of SITCR is valid only when bits FL3 to FL0 in SIMDR are set to 1xxx (x: any value).
SITCR is initialized by the conditions shown in table 22.3, Register State in Each Operating
Mode, or by a transmit reset by the TXRST bit in SICTR.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SITC0[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
SITC1[15:0]
Initial value: — — — — — — — — — — — — — — — —
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W
31 to 16 SITC0[15:0] H'0000 R/W
15 to 0 SITC1[15:0] H'0000 R/W
Description
Control Channel 0 Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as control channel 0 transmit data. The
position of the control channel 0 data in the transmit or
receive frame depends on the value set in the CD0A bit
in SICDAR.
• These bits are valid when the CD0E bit in SICDAR
is set to 1.
Control Channel 1 Transmit Data
These bits specify data to be output from the
SIOF_TXD pin as control channel 1 transmit data. The
position of the control channel 1 data in the transmit or
receive frame depends on the CD1A bit in SICDAR.
• These bits are valid when the CD1E bit in SICDAR
is set to 1.
Rev.1.00 Jan. 10, 2008 Page 1110 of 1658
REJ09B0261-0100