SH7785 Datasheet, PDF (66/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

2. Programming Model
(4) Floating-Point Status/Control Register (FPSCR)
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FR SZ PR DN
Cause
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
R/W: R R R R R R R R R R R/W R/W R/W R/W R/W R/W
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Cause
Enable (EN)
Flag
RM
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 22 —
All 0 R
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
21
FR
0
R/W Floating-Point Register Bank
0: FPR0_BANK0 to FPR15_BANK0 are assigned to
FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1
are assigned to XF0 to XF15
1: FPR0_BANK0 to FPR15_BANK0 are assigned to
XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1
are assigned to FR0 to FR15
20
SZ
0
R/W Transfer Size Mode
0: Data size of FMOV instruction is 32-bits
1: Data size of FMOV instruction is a 32-bit register
pair (64 bits)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5.
19
PR
0
R/W Precision Mode
0: Floating-point instructions are executed as
single-precision operations
1: Floating-point instructions are executed as
double-precision operations (graphics support
instructions are undefined)
For relationship between the SZ bit, PR bit, and endian,
see figure 2.5
18
DN
1
R/W Denormalization Mode
0: Denormalized number is treated as such
1: Denormalized number is treated as zero
Rev.1.00 Jan. 10, 2008 Page 36 of 1658
REJ09B0261-0100