SH7785 Datasheet, PDF (810/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

16. Watchdog Timer and Reset (WDT)
(2) Manual Reset Caused by Watchdog Timer Overflow in Sleep Mode
The timing of indicating the reset state or normal operation on the STATUS[1:0] pins is
synchronous with the peripheral clock (Pck), and is therefore asynchronous with the clocks input
from the EXTAL pin and the CLKOUT pin.
EXTAL
input
CLKOUT
output
CLKOUTENB
output
WDT overflow
signal
MRESETOUT
output
STATUS[1:0]
output
HL (sleep)
HH (reset)
LL (normal)
WDT reset setup time
WDT manual reset holding time
Figure 16.9 STATUS Output by Manual Reset Caused by WDT Overflow
in Sleep Mode
Rev.1.00 Jan. 10, 2008 Page 780 of 1658
REJ09B0261-0100