SH7785 Datasheet, PDF (1037/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

20. Graphics Data Translation Accelerator (GDTA)
20.3.26 MC UV Padding Size Setting Register (MCUVPR)
MCUVPR is in the MC register block and sets the input UV padding size in byte units.
BIt: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯⎯
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯ ⎯
BIt: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
⎯⎯⎯⎯
MC_UVP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: ⎯ ⎯ ⎯ ⎯ R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 12 ⎯
All 0 ⎯ Reserved
These bits are always read as 0. The write value should
always be 0.
11 to 0 MC_UVP All 0 R/W Input UV padding size setting
Should be set by the number of bytes.
Notes: 1. Addition is performed taking that 1 pixel = 1 byte.
2. MCWR (bytes)/2 + MCUVPR (bytes) should be 8 bytes x n (n: an integer greater than
0)
3. MCWR (bytes)/2: Shifts the MCWR setting one bit to the right. (When the setting is odd,
the bit 0 setting is discarded.)
Rev.1.00 Jan. 10, 2008 Page 1007 of 1658
REJ09B0261-0100