SH7785 Datasheet, PDF (873/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

19. Display Unit (DU)
Initial
Internal
Bit
Bit Name Value R/W Update Description
9
DRES
1
R/W None Display Reset
8
DEN
0
R/W Yes
Display Enable
00: Starts display synchronization operation.
In the case of a register not yet set,
unexpected operation may occur; hence
DRES should be set to 0 after setting all the
registers in the display unit (DU).
When DEN = 0, the display data is the value
set in the display-off output register (DOOR).
01: Starts display synchronization operation.
In the case of a register not yet set,
unexpected operation may occur; hence
DRES and DEN should be set to 0 and 1
respectively after setting all the registers in
the display unit (DU).
When DEN = 1, the display data is the value
stored in memory from the next frame.
10: Halts display and synchronization operation.
Halts display operation and synchronization
operation. Except for the following bits in
DSSR, register settings are held.
For these settings, operation is as follows.
1. All display data output is 0.
2. The following bits in DSSR are cleared to
0.
⎯ TV sync signal error flag (TVR)
⎯ Frame flag (FRM)
⎯ Vertical blanking flag (VBK)
⎯ Raster interrupt flag (RINT)
⎯ Horizontal blanking flag (HBK)
3. The HSYNC, VSYNC, ODDF pins are input
pins.
However, when the ODPM bit in DSMR is 1, the
ODDF pin output is clamped.
11: Setting prohibited
Rev.1.00 Jan. 10, 2008 Page 843 of 1658
REJ09B0261-0100