SH7785 Datasheet, PDF (1209/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

24. Multimedia Card Interface (MMCIF)
Bit: 7
6
5
4
3
2
1
0
⎯
⎯
⎯
⎯⎯
⎯
⎯ ^CMD
START
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W
Bit
7 to 1
0
Initial
Bit Name Value R/W
—
All 0 R
CMDSTART 0
R/W
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Starts command transmission when 1 is written. This bit
is automatically cleared to 0 after the MMCIF received
the CMDSTART command. When 0 is written to this bit,
operation is not affected.
24.3.3 Operation Control Register (OPCR)
OPCR is an 8-bit readable/writable register that aborts command operation, and suspends or
continues data transfer.
Bit: 7
6
5
4
3
2
1
0
CMD
OFF
⎯
RD_
CONTI ^DATAEN
⎯
⎯
⎯⎯
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R R/W R/W R
RR
R
Initial
Bit
Bit Name Value R/W Description
7
CMDOFF 0
R/W Command Off
Aborts all command operations (MMCIF command
sequence) when 1 is written after a command is
transmitted. This bit is cleared to 0 automatically after
the MMCIF received the CMDOFF command.
Write enabled period: From command transmission
completion to command sequence end
Write of 0: Operation is not affected.
Write of 1: Command sequence is forcibly aborted.
Note: Do not write to this bit out of the write enable
period.
Rev.1.00 Jan. 10, 2008 Page 1179 of 1658
REJ09B0261-0100