SH7785 Datasheet, PDF (121/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

5. Exception Handling
5.2.2 Exception Event Register (EXPEVT)
The exception event register (EXPEVT) consists of a 12-bit exception code. The exception code
set in EXPEVT is that for a reset or general exception event. The exception code is set
automatically by hardware when an exception occurs. EXPEVT can also be modified by software.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
EXPCODE
Initial value: 0
0
0
0
0
0
0
0
0
0 0/1 0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 12 ⎯
All 0
R
Reserved
For details on reading/writing this bit, see General
Precautions on Handling of Product.
11 to 0 EXPCODE H'000 or R/W Exception Code
H'020
The exception code for a reset or general exception is
set. For details, see table 5.3.
Rev.1.00 Jan. 10, 2008 Page 91 of 1658
REJ09B0261-0100