SH7785 Datasheet, PDF (655/1692 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer

13. PCI Controller (PCIC)
Initial
Bit
Bit Name Value R/W
Description
1, 0
SNPMD All 0 SH: R/W Snoop Mode for PCICSAR0
PCI: —
These bits specify whether PCICSAR0 is compared
with the SuperHyway bus address requested by an
external device, or not. When PCICSAR0 is specified
to be compared, a condition to issue snoop
commands can be specified.
00: PCICSAR0 is not compared
01: Reserved (setting prohibited)
10: PCICSAR0 is compared. If the address matches
PCICSAR0 in the range, snoop commands are
not issued. If not, snoop commands are issued.
11: PCICSAR0 is compared. If the address matches
PCICSAR0 in the range, snoop commands are
issued. If not, snoop commands are not issued.
(25) PCI Cache Snoop Control Register 1 (PCICSCR1)
An external device can access memory of this LSI via the PCIC. When an PCI device accesses a
cacheable area, the PCIC can issue cache snoop commands to the on-chip caches. This register can
specify the function that uses PCICSAR1. For details, see section 13.4.4 (7), Cache Coherency.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
————————————————
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R R R R R
PCI R/W: — — — — — — — — — — — — — — — —
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
———————————
RANGE
SNPMD
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SH R/W: R R R R R R R R R R R R/W R/W R/W R/W R/W
PCI R/W: — — — — — — — — — — — — — — — —
Rev.1.00 Jan. 10, 2008 Page 625 of 1658
REJ09B0261-0100